\hypertarget{group__group2}{\section{Delay Attributes}
\label{group__group2}\index{Delay Attributes@{Delay Attributes}}
}


Delay configuration for the driver.  


\subsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \hyperlink{group__group2_ga9b5018e9d6279fd4f2416aa3891fb106}{S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T}~0x00080808
\begin{DoxyCompactList}\small\item\em Default values specified at baud rate of 62500\-Hz (or higher) for the driver, system clock being 64\-M\-Hz. \end{DoxyCompactList}\end{DoxyCompactItemize}


\subsection{Detailed Description}
Delay configuration for the driver. 

\subsection{Macro Definition Documentation}
\hypertarget{group__group2_ga9b5018e9d6279fd4f2416aa3891fb106}{\index{Delay Attributes@{Delay Attributes}!S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T@{S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T}}
\index{S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T@{S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T}!Delay Attributes@{Delay Attributes}}
\subsubsection[{S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T}]{\setlength{\rightskip}{0pt plus 5cm}\#define S\-P\-I\-\_\-\-D\-E\-L\-A\-Y\-\_\-\-D\-E\-F\-A\-U\-L\-T~0x00080808}}\label{group__group2_ga9b5018e9d6279fd4f2416aa3891fb106}


Default values specified at baud rate of 62500\-Hz (or higher) for the driver, system clock being 64\-M\-Hz. 

This 32-\/bit value is an example for setting delay value characteristics of the driver. This example is set for a baud rate of 62500\-Hz, it can be used for higher baud rates (not optimal though). This value is defined relative to the M\-P\-C5604\-B doc as\-:\par
 -\/bits \mbox{[}3\-:0\mbox{]}\-: T\-D, after transfer delay(0 to F),\par
 -\/bits \mbox{[}7\-:4\mbox{]}\-: P\-T\-D, prescaler for after transfer delay(0 to 3),\par
 -\/bits \mbox{[}11\-:8\mbox{]}\-: A\-S\-C, after S\-C\-K delay(0 to F),\par
 -\/bits \mbox{[}15\-:12\mbox{]}\-: P\-A\-S\-C, prescaler for after S\-C\-K delay(0 to 3),\par
 -\/bits \mbox{[}19\-:16\mbox{]}\-: C\-S\-S\-C\-K, C\-S to S\-C\-K delay(0 to F),\par
 -\/bits \mbox{[}23\-:20\mbox{]}\-: P\-C\-S\-S\-C\-K, prescaler for C\-S to S\-C\-K delay(0 to 3),\par
 -\/bits \mbox{[}31\-:24\mbox{]}\-: unused.\par
\par


Minimum C\-S\-S\-C\-K, A\-S\-C and T\-D values has to be half a S\-C\-K clock period for M\-P\-C5604\-B, on the other hand, external devices may have different needs, so the final values must be the maximum of the minimum values needed by both M\-P\-C5604\-B and the external device.\par
\par


Example for M\-P\-C5604\-B communicating with itself @ 62500\-Hz, a period is 1024 clock cycles when F\-\_\-periph=F\-\_\-sys = 64\-M\-Hz so half a clock is 512 cycles. This value can be set using a prescaler of 1 (0) and a value of 512 (8) for each delay. 

Definition at line 204 of file spi\-\_\-drv.\-h.

